Single SPI Interface
Simplifies DAC and ADC SPI routing through one upstream connection to the host controller, reducing the need for separate interface pins.
Software Flexibility
Provides 16 bit voltage sensing across 16 channels with simultaneous acquisition for accurate and synchronized measurement results.
Built-in Automation
Uses a single SPI bus to support flexible channel expansion while minimizing the need for interface redesign as the system scales.
Why XEIC?
The Problem It Solves
The Challenge
Managing multiple DACs and ADCs requires complex SPI routing, more host-controller pins, and additional firmware to maintain synchronized operation.
The XEIC Solution
XEIC manages one DAC and two ADCs internally in parallel through a single upstream SPI bus, simplifying system design and integration.
Less Wiring, Same Performance
XEIC consolidates three separate SPI device connections into a single SPI bus, reducing host controller pin usage by up to 67% while supporting 32 channels of control and measurement.
METRIC | WITHOUT XEIC | WITH XEIC |
|---|---|---|
Total channels managed | - | 32 channels (16 control + 16 simultaneous measurement) |
Number of separate converter ICs | 3 ICs (1 DAC + 2 ADCs) | Still 3 ICs, but managed by 1 controller |
Number of SPI buses to host controller | 3 separate SPI buses | 1 SPI bus |
Estimated host controller pins* | ~12+ pins | 4 pins (SCLK, MOSI, MISO, CS) |
Estimated host pin reduction | - | Up to ~67% fewer |
How It Works
Key Specifications
KEY SPECIFICATIONS | DETAILS |
|---|---|
Voltage Control Channels | 16 channels |
Voltage Measurement Channels | 16 channels (simultaneous) |
Host Interface | Single upstream SPI bus |
Internal Converters Managed | 1× DAC, 2× ADCs |
Optional Add-On | Analog Front End (AFE) for extended interfacing to Device Under Test (DUT) |